1. Field of the Invention
The present invention relates generally to integrated circuit device electrodes formed within integrated circuits. More particularly, the present invention relates to low contact leakage and low contact resistance integrated circuit device electrodes efficiently formed within integrated circuits.
2. Description of the Related Art
As integrated circuit technology has advanced, and integrated circuit device and conductor element dimensions have decreased, it has become increasingly important to form within advanced integrated circuits integrated circuit devices whose electrodes exhibit low contact leakage and low contact resistance. There are several factors of integrated circuit device electrode design and fabrication which influence the contact leakage and the contact resistance of those integrated circuit device electrodes. Included among the factors are: (1) the presence and thickness of a low contact resistance layer and/or a barrier layer separating the integrated circuit device electrode from a conductor element subsequently formed upon the integrated circuit device electrode; (2) the contact resistance of the material from which is formed the integrated circuit device electrode, the low contact resistance layer and/or the barrier layer, and (3) the overlap distance of a conductor element subsequently formed upon the integrated circuit device electrode.
With regard to the presence and thickness of a low contact resistance layer formed upon the integrated circuit device electrode, it is common in the art of integrated circuit fabrication to form upon the surfaces of integrated circuit device electrodes metal silicide layers which provide low contact resistance layers through which may be formed low contact resistance connections when subsequently forming conductor elements upon those integrated circuit device electrodes. Such metal silicide layers are often formed in a self-aligned fashion to yield an integrated circuit structure analogous to the integrated circuit structure whose schematic plan-view diagram is illustrated in FIG. 1A and whose schematic cross-sectional diagram is illustrated in FIG. 1B.
Shown in FIG. 1A is a schematic plan-view diagram of an integrated circuit prior to forming upon its surface a patterned first conductor layer. Shown in FIG. 1A is a patterned Pre-Metal Dielectric (PDM) layer 24 having a pair of contact vias 25a and 25b formed therethrough which access a pair of exposed metal silicide layers 22a' and 22c'. The pair of exposed metal silicide layers 22a' and 22c' is formed within and upon an active region 11 of a semiconductor substrate within and upon which is formed the integrated circuit. The pair of exposed metal silicide layers 22a' and 22c' is separated by a gate electrode 16 which is also formed upon the active region 11 of the semiconductor substrate.
Corresponding with FIG. 1A, there is shown in FIG. 1B a schematic cross-sectional diagram of the integrated circuit after forming upon its surface a patterned first conductor layer. Shown in FIG. 1B is a semiconductor substrate 10 having formed therein an active region (corresponding with the active region 11 within FIG. 1A) defined by isolation regions 12a and 12b. Within and upon the active region of the semiconductor substrate 10 is formed a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprises a gate oxide layer 14 upon which is formed and aligned a gate electrode 16, as well as a pair of insulator spacers 18a and 18b and a pair of source/drain electrodes 20a and 20b adjoining a pair of opposite edges of the gate oxide layer 14 and the gate electrode 16. Each source/drain electrode within the pair of source/drain electrodes 20a and 20b incorporates a Lightly Doped Drain (LDD) low dose ion implant structure formed within the semiconductor substrate 10 beneath the corresponding insulator spacer 18a or 18b. Upon the surfaces of the source/drain electrode 20a, the gate electrode 16 and the source/drain electrode 20b are formed, respectively, patterned metal silicide layers 22a, 22b and 22c. The patterned metal silicide layers 22a, 22b and 22c are typically, although not exclusively, formed through a self-aligned method whereby portions of a blanket metal silicide forming metal layer in contact with the exposed surfaces of the source/drain electrodes 20a and 20b, and the gate electrode 16, are annealed to form the patterned metal silicide layers 22a, 22c and 22b, respectively. Excess unreacted portions of the blanket metal silicide forming metal layer are typically removed through selective etching methods as are common in the art. Formed then upon the semiconductor substrate 10 is a series of patterned Pre-Metal Dielectric (PMD) layers 24a, 24b and 24c which form a pair of contact vias (corresponding with the pair of contact vias 25a and 25b illustrated within FIG. 1A) which access the surfaces of the metal silicide layers 22a and 22c. Finally, there is formed into the contact vias the patterned barrier layers 26a and 26b upon which are formed and aligned the corresponding patterned first conductor layers 28a and 28b. The patterned first conductor layers 28a and 28b, and the patterned barrier layers 26a and 26b are typically formed through sequential patterning of a blanket first conductor layer which is formed upon a blanket barrier layer.
Although integrated circuits similar to the integrated circuit whose schematic plan-view diagram is illustrated in FIG. 1A and whose schematic cross-sectional diagram is illustrated in FIG. 1B have become common in the art of integrated circuit design and fabrication, integrated circuits similar to the integrated circuit whose schematic plan-view diagram is illustrated in FIG. 1A and whose schematic cross-sectional diagram is illustrated in FIG. 1B are not entirely without problems in forming low contact leakage and low contact resistance connections between the source/drain electrodes 20a and 20b, and the corresponding patterned first conductor layer 28a or 28b. Contact leakage between the patterned first conductor layers 28a and 28b and the corresponding source/drain electrode 20a or 20b is typically enhanced as the as the aspect ratio of the contact vias 25a and 25b between the patterned Pre-Metal Dielectric (PMD) layers 24a, 24b and 24c increases since it becomes increasingly difficult to form uniform barrier layers, such as patterned barrier layers 26a and 26b, of adequate thickness at the bottoms of higher aspect ratio contact vias. In addition, in spite of the low contact resistance provided by the patterned metal silicide layers 22a and 22c, the contact resistance between the source/drain electrodes 20a and 20b, and the corresponding patterned first conductor layer 28a or 28b, is also increased when the width, W1, of the contact vias 25a and 25b between patterned Pre-Metal Dielectric (PMD) layers 24a, 24b and 24c plus two times the registration tolerance of the fabrication tool employed in forming the contact vias 25a and 25b between the patterned Pre-Metal Dielectric (PMD) layers 24a, 24b and 24c is greater than the width, W2, of the patterned metal silicide layer 22a or 22c. Under such conditions, a mis-registration may occur between the patterned first conductor layer 28a and the source/drain electrode 20a and/or the patterned first conductor layer 28b and the source/drain electrode 20b. The increased contact resistance caused by such mis-registration may lead to immediate functionality problems or longer term reliability problems within an integrated circuit analogous to the integrated circuit whose schematic plan-view diagram is illustrated in FIG. 1A and whose schematic cross-sectional diagram is illustrated in FIG. 1B.
Finally, although somewhat indirectly related to contact resistance and contact leakage, the integrated circuit whose schematic plan-view diagram is illustrated in FIG. 1A and whose schematic cross-sectional diagram is illustrated in FIG. 1B also typically requires for its formation two separate blanket metal layers which are employed in providing low contact leakage and low contact resistance connections to the source/drain electrodes 20a and 20b within the integrated circuit. The two separate blanket metal layers are: (1) the blanket metal silicide forming metal layer which is employed in forming the patterned metal silicide layers 22a, 22b and 22c, and (2) a second blanket metal layer which is typically employed in forming, at least in part, the patterned barrier layers 26a and 26b. Since the patterned metal silicide layers 22a, 22b and 22c, and the patterned barrier layers 26a and 26b may often be formed from metal layers which are formed from the same metal, such as but not limited to titanium metal and tungsten metal, there exists the possibility of increased manufacturing efficiency under circumstances where the functions of blanket metal silicide forming metal layer and the second blanket metal layer from which is formed the patterned barrier layers 26a and 26b may be provided with one, rather than two, blanket metal layers.
As is understood by a person skilled in the art, analogous contact leakage increases and contact resistance increases may occur within integrated circuits having formed therein integrated circuit devices other than Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) (ie: integrated circuits other than the integrated circuit whose schematic plan-view diagram is shown in FIG. 1A and whose schematic cross-sectional diagram is shown in FIG. 1B), under circumstances where: (1) the width of the integrated circuit device electrode within the integrated circuit device is less than the width of a conductor element desired to be formed upon the integrated circuit device electrode plus two times the registration tolerance of a fabrication tool employed in defining the location of the conductor element, and (2) the width of the integrated circuit device electrode within the integrated circuit device cannot readily be increased.
It is thus towards the goal of forming within integrated circuits analogous to the integrated circuit whose schematic plan-view diagram is illustrated in FIG. 1A and whose schematic cross-sectional diagram is illustrated in FIG. 1B integrated circuit device electrodes which provide the desirable low contact resistance of conductor element connections formed upon metal suicide layered integrated circuit device electrodes, while simultaneously minimizing: (1) increases in contact leakage due to barrier layer thinning upon those integrated circuit device electrodes, and (2) increases in contact resistance due to mis-registration of conductor elements formed upon those integrated circuit device electrodes, that the present invention is generally directed.
The general and conventional self-aligned method for forming metal suicide layered integrated circuit device electrodes is disclosed by S. Wolf et al. in Silicon Processing for the VLSI Era, Vol. 1--Process Technology, Lattice Press (Sunset Beach, Calif., 1986) pp. 397-99.
In addition, several other methods through which conductor elements and electrodes having novel and desirable properties may be formed within integrated circuits have also been disclosed in the art. For example, Moritz, in U.S. Pat. No. 4,378,383 discloses a lift-off method employing an undercut photoresist layer for forming conductive interconnection studs within an insulator layer within an integrated circuit. In addition, Ehara et al., in U.S. Pat. No. 4,448,800 disclose a lift-off method which employs a patterned refractory metal layer as a mask layer in order to limit particulate contamination within a lift-off process employed in forming integrated circuits. Further, Ayoama et al., in U.S. Pat. No. 4,520,041 disclose a method for forming a substantially flat metallization structure on the surface of a semiconductor substrate. Yet further, Gigante et al., in U.S. Pat. No. 4,532,702 disclose a method for selectively forming tungsten interconnection studs within insulator layers within integrated circuits. Still further, Deleonibus et al., in U.S. Pat. No. 4,592,802 disclose yet another method and associated materials for fabricating interconnection studs within insulator layers within integrated circuits.
Most pertinent to the goals towards which the present invention is directed, however, is the disclosure of Jeuch et al., in U.S. Pat. No. 4,544,445. Jeuch et al. disclose a method for positioning an interconnection line on a contact hole accessing an integrated circuit device electrode within an integrated circuit. The disclosed method employs forming at least one conductor layer upon the contact hole which is defined through an insulator layer, and subsequently patterning the conductor layer(s) to form an interconnection line in contact with the integrated circuit device electrode at the bottom of the contact hole.
Desirable in the art are additional methods for forming integrated circuit device electrodes upon which may subsequently be formed conductor elements within integrated circuits. Particularly desirable are methods which provide an integrated circuit device electrode to which may be formed a low contact leakage and a low contact resistance connection with a conductor element within the integrated circuit. Most particularly desirable are methods which provide an integrated circuit device electrode to which may be formed a low contact leakage and a low contact resistance connection with a conductor element within the integrated circuit while employing a minimal number of blanket metal layers in providing the integrated circuit layers which provide the low contact leakage and low contact resistance connection.